Embodiments of the inventive subject matter generally relate to the field of circuit design, and, more particularly, to timing analysis of asynchronous clock domain crossings.
Computer chips and systems-on-chips may include multiple systems and sub-systems. Each of these systems and sub-systems may include multiple “clock domains.” A clock domain is a set of sequential logic elements, such as transparent latches and flip-flops, and combinational logic associated with these sequential logic elements that are clocked by a common clock or by clocks having common frequency and a fixed phase relationship. A clock signal causes a change in the state of sequential logic, such as a flip-flop, latch, register, etc. A clock domain crossing is a path from a sequential logic element, or other source of state transitions in a design, in a first clock domain to a sequential logic element in a second clock domain. The clock in the first clock domain may operate asynchronously with respect to the second clock domain. In such cases, when a data signal path crosses from the first clock domain to the second clock domain, the crossing is referred to as an “asynchronous clock domain crossing.” The term “asynchronous” indicates that there is no fixed relationship between the phase of a first clock in the first clock domain and the phase of a second clock in the second clock domain.